In general, in a complementary metal-oxide-semiconductor (CMOS) device, the gate leakage current is five times greater in an n-type metal-oxide-semiconductor (NMOS) region than in a p-type metal-oxide-semiconductor (PMOS) region, and the transistor channel current is two times greater in a NMOS region than in a PMOS region due to the difference in the mobility of charges and holes. Normally, in order to improve the transistor channel current in the PMOS region, which is recessive in terms of the transistor channel current, the width of the PMOS region is increased. However, this method has limitations with regards to the integration of the CMOS device.
Meanwhile, the transistor channel current in a PMOS region can be improved by forming a thinner gate insulating layer for a PMOS region than for an NMOS region. This method is advantageous because the gate leakage current of the PMOS region is lower than that of the NMOS region. However, modifying the thicknesses of the gate insulating layers of the PMOS region and the NMOS region MA may be complicated. That is, it can be difficult to first form gate insulating layers to the same thickness in the PMOS region and the NMOS region and then to modify the thickness of the gate insulating layers through a patterning process in which a predetermined region of the gate insulating layers is selectively exposed. This process has another disadvantage in that manufacturing costs of the semiconductor device increase.